The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 1996

Filed:

Apr. 07, 1994
Applicant:
Inventors:

Larry D McMillan, Colorado Springs, CO (US);

Takashi Mihara, Saitama, JP;

Hiroyuki Yoshimori, Kanagawa, JP;

John W Gregory, Colorado Springs, CO (US);

Carlos A Paz de Araujo, Colorado Springs, CO (US);

Assignees:

Symetrix Corporation, Colorado Springs, CO (US);

Olympus Optical Co., Ltd., , JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
365145 ; 365117 ; 257295 ;
Abstract

An integrated circuit non-volatile, non-destructive read-out memory unit includes a ferroelectric capacitor having first and second electrodes, a capacitance Cf, and an area Af, and a transistor having a gate, a source and a drain forming a gate capacitor having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a, with the capacitor first electrode connected to the gate of the transistor. The ferroelectric material has a dielectric constant .epsilon.f and the gate insulator has a dielectric constant .epsilon.g. A source of a constant reference voltage is connectable to the first electrode. A bit line connects to the second electrode. In one embodiment the first electrode and gate are the same conductive member. In another embodiment the second electrode and the gate are the same conductive member and the first electrode is formed by extensions of the transistor source and drains underlying the gate, with the ferroelectric material between the source and drain extensions and the gate. The memory unit has the parametric relationships: Cf<5.times.Cg, Af.ltoreq.2Ag, b.gtoreq.2a, and .epsilon.g.gtoreq..epsilon.f/8.


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