Image processor with input buffering to multiple digital signal

Abstract

A system architecture is provided that includes an image sensor unit operable in a single channel mode and a dual channel mode. The image sensor unit includes an electronic image sensor comprising a row and column array of pixel elements, wherein the rows of the array having a line length of N pixels. First and second digital signal processing units for processing image data generated by the image sensor unit into color component image data are provided, wherein each of said first and second digital signal processing units has a line length processing capacity less than N pixels. An input buffer, coupled between outputs of the image sensor unit and inputs to the digital signal processing units, simultaneously receives two lines of image data from the image sensor unit in the dual channel mode of operation, and sequentially supplies a first portion of each of the simultaneously received image lines to the first digital signal processing unit and a second portion of each of the simultaneously received image lines to the second digital signal processing unit. An output buffer, coupled to the output of the first and second digital signal processing units, combines the color component image data generated by the first and second digital signal processing units into color component image lines of length N pixels. A control unit controls the operation of the image sensor unit, the input buffer, the first and second digital signal processing units, and the output buffer. A frame store receives and stores the color component image lines generated by the output buffer, and a monitor displays the image lines at a frame rate that is about twice the operating frame rate of the image sensor unit.