Multiplex circuit arrangement for use with a semiconductor integrated

Abstract

A multiplex circuit is disclosed in which a plurality of bipolar transistors are combined and in which the respective base terminals thereof are used as inputs, thereby to construct an emitter follower type multiplex circuit. In such an emitter follower type multiplex circuit, the multiplexing function of non-selection/selection is effected by controlling the base potential of the respective bipolar transistors by providing a MOS transistor between each base and a high potential of the power source through a resistor and a current drawing circuit. In accordance with such a scheme, when a selection of one input signal is made, the bipolar transistor corresponding thereto is permitted to turn ON on the basis of an input signal supplied to the base terminal thereof. The bipolar transistors corresponding to the non-selection input signals are maintained OFF, through activating the current drawing circuits associated therewith, irrespective of the potential levels of the incoming input signals supplied to the base terminals thereof. In the emitter follower type multiplex circuit, a constant current source is also provided between the commonly connected emitters of the bipolar transistors and the power source of low potential. The multiplex arrangement effected can be of the collector dot type multiplex circuit. Such multiplex circuits are used with a semiconductor integrated circuit such as a memory circuit.