The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 1996

Filed:

Aug. 26, 1993
Applicant:
Inventors:

Fusen E Chen, Dallas, TX (US);

Robert O Miller, The Colony, TX (US);

Girish A Dixit, Dallas, TX (US);

Assignee:

SGS-Thomson Microelectronics, Inc., Carrollton, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257751 ; 257754 ; 257763 ; 257764 ; 257767 ; 257915 ;
Abstract

A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.


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