The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 1996
Filed:
Oct. 29, 1993
Mitchell G Burton, Burnaby, CA;
Mark J Wilson, Burnaby, CA;
Sierra Semiconductor Canada, Inc., Vancouver, CA;
Abstract
A mechanism is provided for software configuration of ISA bus cards or other devices connected to a computer processor by a bus that does not provide for sharing of an address by multiple devices. Such a device is configured under software control by selecting multiple addresses commonly used by a read-only device, writing from the computer processor to the configuration logic at one of such addresses a predetermined data word as part of a predetermined security access sequence, writing from the computer processor to the configuration logic at one of the addresses configuration information including a device based address, and the configuration logic, in response to the predetermined security access sequence, storing the configuration information in configuration registers, thereby configuring the device. The addresses used may be addresses used by a game device, such as a joystick. An apparatus for configuring such a device includes multiple configuration registers, circuitry for qualifying access to the configuration registers by verifying compliance with the predetermined security access sequence, the predetermined security access sequence including the central processor writing a predetermined data word to the configuration logic at one of multiple addresses commonly used by a read-only device, and circuitry for, in response to the predetermined security access sequence, storing in the configuration registers configuration information written by the computer processor to one of the multiple addresses, the configuration information including a device base address.