The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 1996

Filed:

Nov. 30, 1993
Applicant:
Inventor:

Glen E Offord, Macungie, PA (US);

Assignee:

AT&T Corp., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
395280 ; 375354 ; 375362 ;
Abstract

An asynchronous to synchronous interface between a master chip and a target chip, the interface being located on the target chip, includes a synchronous write logic unit and one set of synchronous transfer latches. A system clock (clock on target chip) and asynchronous clock signal are connected to the synchronous write logic unit. The asynchronous clock signal is also connected to a set of asynchronous latches, which receive data from the master chip upon receiving active asynchronous clock signals. The asynchronous latches are connected to a set of synchronous latches. The synchronous latches are controlled by a synchronous write signal generated by the synchronous write logic unit. Based on the asynchronous write signal and clock signal of the target chip the synchronous write logic unit synchronously transfers data from the outputs of the asynchronous latches to the outputs of the synchronous latches.


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