The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 1996
Filed:
Jan. 31, 1995
William K Walker, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
This is a system and method of fabricating hybrid integrated circuits (IC). The method may comprise: forming internal IC structures on a substrate; forming IC interlevel insulation on top of the internal IC structures; forming IC top level metal connections on top of the IC interlevel insulation; depositing a protective overcoat over the IC top level metal and the IC interlevel insulation; depositing a dry etch protective layer over the protective overcoat; and dry etching the etch protective layer and the protective overcoat to expose portions of the IC top level metal. The deposition of the protective overcoat may include depositing silicon dioxide or silicon nitride. In addition, the deposition of the dry etch protective layer may include depositing a photosensitive polymide layer. Furthermore, the dry etching may include photolithography. After the etching of the vias, the method may include: forming thermal isolation mesas on the substrate; forming local interconnects over the thermal isolation mesas and the substrate; and connecting uncooled infrared detectors to the internal IC structures through the local interconnects.