The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 1996

Filed:

Jan. 12, 1994
Applicant:
Inventors:

Yasushi Yoneda, Ikeda, JP;

Shinichi Saeki, Sakai, JP;

Noriyuki Hidaka, Moriguchi, JP;

Minobu Abe, Hirakata, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
395800 ; 3642293 ; 3642295 ; 3642306 ; 3642314 ; 3642341 ; 364239 ; 3642387 ; 3642416 ; 3642591 ; 3642592 ; 3642596 ; 3642704 ; 3642715 ; 364271 ; 3642719 ; 364D / ; 364D / ; 395550 ;
Abstract

Disclosed is an apparatus of synchronizing parallel processing among a plurality of processors including a plurality of synchronization units respectively corresponding to the plurality of processors and a control unit. The control unit and the synchronization units are connected in a loop. Each synchronization unit outputs a sync signal for informing that the synchronization unit has entered a wait state to an adjacent downstream unit. The control unit outputs a pulse for informing a completion of a synchronization among the processors to an uppermost-stream synchronization unit. The pulse is forwarded as far as an lowermost-stream synchronization unit. Each synchronization unit includes the following: a flag hold unit holding a flag indicating a state of a respective processor, a logical OR circuit ORing a sync signal sent from an adjacent upstream synchronization unit with a value of the flag and outputting an obtained value to an adjacent downstream synchronization unit as a sync signal, a detection unit detecting the pulse in a value outputted from the logical OR circuit, thereby initiating the flag hold unit, and an output unit outputting the value outputted from the logical OR circuit to a respective processor.


Find Patent Forward Citations

Loading…