The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 1996
Filed:
Dec. 09, 1994
Anthony C Barkans, Fort Collins, CO (US);
Bryan G Prouty, Wellington, CO (US);
Lawrence G Mahoney, Fort Collins, CO (US);
Ian A Elliott, Fort Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
First next and second next pixel locations are selected simultaneously from among adjacent pixel locations and represent a straight line segment defined by two end locations and having a slope of one or less. An initialization process uses the .DELTA.X and .DELTA.Y of the desired line segment to find various constants, including an initial error term, an error term increment, an error term decrement, an error term double increment, an error term double decrement, and an error term increment-then-decrement. These represent, respectively, an increment in the X location without an increment to the Y location (a step S), an increment in the X location and an increment in the Y location (a jump J), a step followed by a step (two steps SS), two jumps (JJ), and either of a step-then-jump or a jump-then-step (SJ/JS). These five operations correspond to the only possible locations that might be selected, given any starting location. Of the five operations, exactly one of the first two will be for the first next location, while exactly one of the last three will be for the second next location. The present error term is an input to three different adders. Another input to each of the adders is one of the constants for S or J and two of the constants for SS, JJ and SJ/JS. The three additions proceed simultaneously. The initial error term and the resulting three trial error terms can be inspected in relation to error term limits. When the Bresenham Algorithm is implemented, these comparisons are simple determinations of sign. A logic circuit responsive to the error term inspection indicates which combination of the operations S and J correspond to the desired path. A corresponding frame buffer operation code is sent to the a frame buffer address controller. Once the selection is made the error term value for the selected second next pixel location is captured and made to be the error term input for the adders, and the process is ready to select another two pixel locations. If .DELTA.X is an odd number then the second next position is not needed for the final sequence of frame buffer operation codes, and it to be suppressed.