The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 1996
Filed:
Feb. 21, 1995
Dennis N Eddlemon, Tucson, AZ (US);
Apex Microtechnology, Tucson, AZ (US);
Abstract
A biasing arrangement for a quasi-complementary output stage having first and second transistors of a first type, where at least one of the transistors is driven by a third transistor of a second type. The inventive biasing arrangement comprises a first circuit for biasing the third transistor and a second circuit having a third circuit for providing an input signal to the first transistor and a fourth circuit for providing the input signal to the first circuit. In a particular implementation, the first circuit is connected between the input terminals of the first and the third transistors. The third circuit is a fourth transistor having a first terminal connected to a first source of supply, a second terminal connected to a source of the input signal and a third terminal connected to a second source of supply. The third terminal of the fourth transistor is connected to the second source of supply via a first resistor. The fourth circuit is a fifth transistor having a first terminal connected to an input terminal of the third transistor, a second terminal connected to the source of the input signal, and a third terminal connected to the third terminal of the fourth transistor. The inventive arrangement provides a symmetrical output signal with a bias that is stable with temperature.