Two channel direct digital synthesizer with waveform memory interleaving

Abstract

A two channel direct digital synthesis circuit employing a waveform interleaving circuit is provided. A clock having first and second states controls the overall operation of the memory interleave operation. A phase accumulator is incremented by a phase increment value according to a clock rate. The phase accumulator value is provided to a first multiplexer and to an offset adder where the first multiplexer selects between the phase accumulator value and the sum of the phase accumulator value and a phase offset value. First and second waveform select signals are provided to the inputs of a second multiplexer where the second multiplexer selects between the first and second waveform select signals. The outputs of the first and second multiplexers form an address which is coupled to a waveform memory containing first and second digital waveform patterns. Digital waveform data according to the first and second digital waveform patterns from the waveform memory is provided to first and second latches which store the data responsive to the first and second waveform select signals. The digital waveform data from the first and second latches are provided to first and second digital to analog converters to produce first and second output waveforms which have a phase offset according to the phase offset value.