The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 1996

Filed:

May. 05, 1995
Applicant:
Inventors:

John A Bracchitta, South Burlington, VT (US);

Gabriel Hartstein, Burlington, VT (US);

Stephen A Mongeon, Essex Junction, VT (US);

Anthony C Speranza, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 44 ; 437 / ; 437 40 ; 437149 ; 437153 ; 437154 ; 437160 ; 437164 ; 148D / ;
Abstract

A method of fabricating a lightly doped drain MOSFET device with a built in etch stop is disclosed. After forming a gate electrode on a substrate through conventional methods, a conformal doped layer is deposited on the gate electrode. A conformal layer of nitride is then deposited on the conformal doped layer. The nitride layer is etched, with the etch stopping on the conformal doped layer, thereby forming nitride spacers. Deep source and drain regions are formed by either ion implantation or diffusion. The device is then heat treated so that light diffusion occurs under the nitride spacers and heavy diffusion occurs outside the spacer region. The method is applicable to N-substrate (P-channel), P-substrate (N-channel), and complementary metal oxide semiconductor (CMOS) devices.


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