Standing sine wave clock bus for clock distribution systems

Abstract

A clock phase and frequency distribution system is disclosed which uses a standing sine wave and provides substantially simultaneous significant crossing instances everywhere in the system while using low power and not requiring bus termination or precise control of transmission path characteristics (Z.sub.0). The system is particularly advantageous in high frequency applications such as digital, linear (non-branched), backplane applications, but is also applicable to other topographies such as stars, rings, and meshes. The system includes a sine wave generating and driving circuit, a clock bus, and clock receivers. The clock receivers present a high impedance interface to the clock bus. The basic design considerations and parameters which limit and define performance include the maximum propagation delay between any two points in the system, the total low frequency capacitance of the system, and the Q of the system which must be high at the frequency of the standing wave in order to satisfy low power and simultaneity objectives. To overcome system length limitations, embodiments utilizing master and slaves are provided, where phase feedback is provided to the slaves. Multifrequency systems are also provided.