The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 1996

Filed:

Jun. 07, 1994
Applicant:
Inventors:

David C Andreas, West Chester, PA (US);

Jon Dattorro, West Chester, PA (US);

J William Mauchly, Berwyn, PA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
364736 ; 364768 ;
Abstract

A digital signal processor for efficiently handling audio applications is disclosed. The single chip digital signal processor includes an on-chip instruction memory for outputting instructions representing an audio application program. Four busses, W, X, Y and Z, provide communication within the processor. An ALU performs a plurality of arithmetic and logical functions according to the instruction memory. Specialized implementations for functions have been specially developed for audio applications, for example, a single cycle average instruction, a jump on condition code instruction, a repeat instruction, a limit instruction. A Multiplier Accumulator/Barrel Shifter performs a plurality of MAC and shifting functions according to the instruction memory. The MAC/BS is coupled in parallel with the ALU and an Address Generator. The Address Generator performs a plurality of address calculation functions according to the instruction memory. Some of the data storage areas include: 1) a GPR memory for writing data to the X and Y busses and reading data from the Z bus; 2) an AOR memory for writing data to the W, X, and Y busses and reading data from the Z bus; and 3) an SPR memory for writing data to and reading data from the X, Y and Z busses and for outputting control information to the ALU, the MAC/BS and the AGEN.


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