The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 1996

Filed:

Jul. 22, 1994
Applicant:
Inventor:

Takashi Mihara, Iruma, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365145 ; 257295 ;
Abstract

A ferroelectric memory having a structure in which source and drain are formed on a semiconductor substrate, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a ferroelectric gate transistor memory cell having a ferroelectric gate transistor structure including a gate electrode made of a conductive gate electrode, is arranged on the thin film. An X selection line (column) is connected to the gate of the memory cell, and a Y selection line (row line) is connected to the source and drain, or the column and row of the X and Y selection line are connected to the memory cell vice versa. The memory can be driven only by 1-transistor/1-cell without a pass gate transistor, and the data can be non-destructively read out by applying a voltage lower than the coercive voltage of the ferroelectric to the gate electrode, the source and drain.


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