The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 1996
Filed:
May. 02, 1995
Fumihiro Watanabe, Hyogo, JP;
Fumihide Murao, Kanagawa, JP;
Hiroshi Murakami, Hyogo, JP;
Hideo Hara, Hyogo, JP;
Hideho Itoh, Hyogo, JP;
Tatsuya Hohmoto, Hyogo, JP;
Mitsubishi Electric Engineering Co., Ltd., Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A current-voltage conversion circuit which is capable of performing logarithmic compression is obtained using only CMOS processes. An emitter of a PNP transistor (10) and a current input terminal (51) are connected commonly to a reverse input terminal of an operational amplifier (53), while a first reference voltage input terminal is connected to a non-reverse input terminal of the operational amplifier (53). A collector of the PNP transistor (10) is grounded and a base of the PNP transistor (10) is connected to an output terminal of the operational amplifier (53) and an output terminal (55). A current (I) is supplied to the current input terminal (51) while a first reference voltage (V.sub.REF1) is applied to the first reference voltage input terminal. The PNP transistor (10) is formed by CMOS processes. The current-voltage conversion circuit is manufactured in a shorter manufacturing time and at a reduced cost.