Method and apparatus for power-up state initialization in a data

Abstract

A method and apparatus for implementing a power-up state initialization. A power sense circuit provides a signal for indicating when the power supply, V.sub.DD, is of a voltage level greater than the minimum voltage level suitable for safely resolving CMOS logic. The power sense signal, when asserted, enables a small, on-chip ring oscillator. An output signal generated by the ring oscillator supplies a clocking signal to the clock drivers and to the clock state machine of the CPU, thereby providing internal clocks to a central processing unit (CPU). A counter counts the number of clock pulses provided to the CPU and disables the ring oscillator and the clock state machine (thereby stopping the internal data-processor clock drivers) when the accumulated number of clock pulses equals or exceeds a predefined number. The predefined number of internal clock pulses is the minimum number of clocks to process a reset condition that resolves all on-chip, CPU state conflicts and contention.