The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 1996
Filed:
Jun. 21, 1995
Wesley Moore, Morrisville, NC (US);
Ward Huffman, Durham, NC (US);
Mitsubishi Semiconductor America, Inc., Durham, NC (US);
Abstract
A set of logic cells is hierarchically grouped to form groups to be placed on an integrated circuit for gate array layout. A user interface allows a user to interact with a placement system. The system is supplied with input design files defining the integrated circuit, the cells to be grouped, the groups to be placed, and input/output buffers to be placed on the perimeter of the integrated circuit for connecting the groups with external circuitry. The system reads the input design files to create a database used for placing desired input/output buffers and for hierarchically grouping the cells and placing the groups. The groups are defined by their size, determined using utilization and aspect ratio values of the areas where the cells are to be placed. The user is allowed to move the buffers and groups to any valid locations within the integrated circuit.