The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 1996

Filed:

Oct. 07, 1994
Applicant:
Inventors:

Norio Ueno, Kawasaki, JP;

Toru Matsuyama, Sapporo, JP;

Assignee:

Fujitsu Limited, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L / ; H03K / ; H03B / ; H01L / ;
U.S. Cl.
CPC ...
327333 ; 327108 ; 327379 ; 327389 ; 327564 ; 327565 ; 327566 ; 326 21 ; 326 23 ;
Abstract

An interface circuit for interfacing between an integrated circuit (IC) on a transmitting side and an IC on a receiving side over a line on a printed circuit board comprises an output circuit implemented in the IC on the transmitting side and composed of a current source for supplying a given current and a switching circuit for cutting off the given current according to a binary signal and delivering the given current as a current signal to the line, and an input circuit implemented in the IC on the receiving side and composed of a transimpedance circuit whose input impedance is equal to the one of the line and which converts the current signal into a voltage signal, and a comparator for identifying the voltage signal relative to a given threshold voltage and reproducing the binary signal. This circuitry makes it possible to provide an interface circuit that can be implemented in a CMOS IC during CMOS processing and operated at a low voltage. A threshold voltage for use in identifying a signal on the receiving side is stabilized, thus realizing an interface circuit unsusceptible to influence of a change in CMOS processing or the like.


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