Semiconductor integrated circuit device

Abstract

A logic block of a memory (LSI) with logic functions includes RAM macrocells (RAMO-RAM7) and a centrally located gate array (GAO-GA5). Clock pulse shaping circuits (CSPO, CSP1) and input/output portion (I/O) surround the logic block. The logic block power supply includes a smoothing capacitor (CC) that is substantially the same size as a cell (GC) of the gate array. Each RAM macrocell has memory mats (MATOO-MAT21), word lines (WO-W127), data lines (DO-D7), and peripheral circuits (MPCOO-MPC21), which includes an address decoder and a sense amp (SAO). An input unit cell (ICO) receives ECL level signals and outputs ECL level signals (FIG. 5 ) and MOS level signals (FIG. 6 ). The input unit cells and analogous output unit cells (OCO) are selectively used singly or in parallel to accommodate signals of different form and driving capability. A wiring line replacement region (LRP) connects memory macrocell wiring lines with logic block wiring lines. A sequence control circuit cell or aligner (ALNO, ALN1) contiguous to the RAM macrocells transmits output signals to the logic block on the wiring lines. A clock signal distribution circuit (CDA) is arranged centrally of the RAM macrocells for distributing ECL level clock signals. The clock signal distribution circuit includes clock switch amplifier circuits (CSAO-CSA9) including bipolar transistors and MOSFETs (FIG. 23 ).