The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 1996
Filed:
Dec. 19, 1994
Joseph E Farb, Riverside, CA (US);
Chen-chi P Chang, Newport Beach, CA (US);
Mei F Li, Mission Viejo, CA (US);
Hughes Aircraft Company, Los Angeles, CA (US);
Abstract
Each unit cell (10) of a flash EEPROM array (50) includes a source (18), a drain (20) and a channel (22) formed in a substrate (12). A thin tunnel oxide layer (32) is formed over the substrate (12) and P-Well (14). A bifurcated floating gate (34) is formed on the tunnel oxide layer (32) overlying the channel (22) , and includes a program arm (34a) which overlaps the drain (20), an erase arm (34b) which overlaps the source (18) and a base (34c) which extends around an end of the channel (22) and interconnects the program and erase arms (34a,34b). A thick gate oxide layer (36,36a) is formed over the floating gate (34), and a control gate (38) is formed over the gate oxide layer (36,36a). A central section of the control gate (38) which overlies a gap (34d) between the program and erase arms (34a, 34b) provides threshold voltage control for erasure. The erase arm (34b) spans the entire width of the channel (22), enabling erasure with low applied voltages. The bifurcated floating gate design automatically compensates for alignment error during fabrication such that the relative areas of the channel (22) which underlie the program/erase arms (34a, 34b) and gap (34d) are independent of the location of the gap (34d).