The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 1996
Filed:
Dec. 15, 1993
John Brennan, Mountain View, CA (US);
Peter Y Hsu, Fremont, CA (US);
William A Huffman, Los Gatos, CA (US);
Paul Rodman, Palo Alto, CA (US);
Joseph T Scanlon, Sunnyvale, CA (US);
Man K Tang, Milpitas, CA (US);
Steve J Ciavaglia, Williston, VT (US);
Silicon Graphics, Inc., Mountain View, CA (US);
Abstract
A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.