Reset and clock circuit for providing valid power up reset signal prior

Abstract

A reset and clock circuit for providing a valid power-up reset signal prior to distribution of a clock signal includes power sensing circuitry, a clock generator and a reset generator. The power sensing circuitry monitors the power supply voltage and generates a power-up signal which is asserted when it has risen above a predetermined value. The power sensing circuitry also receives a clock signal and, in accordance with the power-up and clock signals, provides a number of power status signals. One of the power status signals is asserted in response to assertion of the power-up signal, while another is asserted in response to reception of a group of clock signal pulses. The clock generator, in response to assertion of the first power status signal, provides the clock signal. The reset generator, in accordance with the power status signals and clock signal, provides a number of reset signals each one of which is initially asserted prior to the providing of the clock signal by the clock signal generator. One of the reset signals is de-asserted in response to reception of another group of clock signal pulses, while another is de-asserted in response to reception of still another group of clock signal pulses.