The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 1996

Filed:

Oct. 05, 1994
Applicant:
Inventor:

Hideki Hara, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 43 ; 437984 ;
Abstract

Gate insulating film of a memory cell in a nonvolatile semiconductor memory devices is protected from a plasma damage by a residual side wall insulating film. After forming field oxide films and first gate insulating films, gate structures each including a control gate, a second insulating film and a floating gate is formed. A fourth insulating films are deposited on the entire surface and ion-etched to leave residual side wall insulating films at the side walls of each of the gate structures. The residual side wall films protect the first gate insulating films and silicon substrate from a plasma damage. At least one of the source and drain is formed in a LDD structure due to the ion-implantation through the residual side wall insulating films. Resistance characteristics to breakdown due to a high voltage can be improved by reducing deterioration of the first gate insulating films. Other electric characteristics can be improved by the LDD structure.


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