The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 1996

Filed:

Sep. 26, 1994
Applicant:
Inventor:

Takeshi Yamamura, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
371 211 ; 371 225 ; 371 226 ; 39518306 ; 324765 ; 365201 ;
Abstract

A semiconductor integrated circuit includes a chip (10a), a core area (12) on the chip in which tester circuits (14) are placed, and an I/O area (13) on the chip. The I/O area is provided at the periphery of the core area, and in the I/O area a plurality of tester circuits (17) are placed for testing the functions of respectively testee circuits in, respectively core area. The I/O area is provided with test control circuits (15) for supplying a control signal (C2) and a clock signal (C3), for testing said tester circuits, to the test circuits and testee circuits, on the basis of an external control signal supplied from outside.


Find Patent Forward Citations

Yamamura, Takeshi. (1996). Semiconductor integrated circuit device having test control circuit in (U.S. Patent No. 5509019). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5509019

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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