The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 1996
Filed:
Jul. 21, 1994
Applicant:
Inventor:
Michael J Shay, Arlington, TX (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H / ;
U.S. Cl.
CPC ...
327318 ; 327 78 ; 327143 ; 361 56 ;
Abstract
A voltage level triggered ESD protection circuit is immune to standard signal transitions up to approximately 5.5 volts, does not consume any DC current either in the powered up or powered down states, and is interfaceable to a live bus when the system it is connected to is powered down. The trigger circuit is reliably immune to tripping from applied fast bus transitions on a powered-down integrated circuit. The trigger signal is generated in response to sensing both a voltage transition and to reaching a voltage set point such as 7 volts, rather than merely triggering off the voltage transition.