Method and apparatus for testing electronic memories for the presence of

Abstract

A method of testing a random access memory (RAM) for single V-coupling faults by establishing a first current value for each cell, for each cell and for each of m data backgrounds, generating a data bit corresponding to an element of an (n, V-1)-exhaustive matrix, and for each of m data backgrounds: (1) applying a read write sequence to each cell; and (2) for each background except the mth background, updating the current value of all cells according to the data bits corresponding to that cell; reading each cell of the RAM; and discarding or repairing the RAM if a cell coupling fault is apparent from the series of values read from the cells of the RAM. Data bits are generated by a matrix reconstruction method or a pseudo-random generator using a hashing of the address of the cell to which the data bit is to be applied. The logical function may be the element of the (n, V-1)-exhaustive matrix irrespective of the current of the cell or an exclusive-or of the complement of the background code logic bit and the first current value of the cell. Apparatus for testing a random access memory (RAM) has a PROM containing background code logic bits corresponding to an (n.sub.0, V-1)-exhaustive matrix where n.sub.0 .ltoreq.n, the matrix having n.sub.0 rows and m.sub.0 columns; and a data bit generator for generating data bits from the matrix stored in the PROM. A built in apparatus for testing a random access memory (RAM) having n cells includes a data bit generator that generates pseudo-random data bits from a hashing of the address of the RAM cell to which the data bit is to be applied.