The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 1996
Filed:
Jun. 30, 1995
Richard E Fry, Round Rock, TX (US);
Troy N Hicks, Austin, TX (US);
Larry E Thatcher, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system that allows the continuous accessing of data on a floating point processor unit (FPU), by providing two data ports and corresponding buses between the data cache and the FPU. Further, synchronization between the fixed point unit (FXU), which provides the addresses, and the FPU is provided so that data can be loaded in the event of a data cache miss. This synchronization allows data to be transferred from the DCU to the FPU independent of an error condition (cache miss) on one of the buses. If a cache miss occurs that affects a first one of the buses, then the instruction corresponding to this data is held. Subsequent floating point data is received by the FPU on the second bus not subject to the miss. Synchronization signals include, load ready (LD1.sub.-- RDY) indicating to the FPU that data is on the bus and ready to be moved to the FPU and load not ready (LD1.sub.-- NRDY) that means a floating point load has executed successfully in the FXU, but due to a cache miss, the data is not yet available to the FPU. The FXU sends an address, along an address bus corresponding to the data bus not affected by the miss, for data in the cache. Thus, even in the case of a data cache miss, the FPU can continue operations by loading data, that has been addressed to the data port which does not correspond to the cache miss.