Programmable clock having programmable delay and duty cycle based on a

Abstract

An input clock delay circuit includes an up counter for estimating the approximate number of internal clock cycles that occur during one cycle of the input clock signal and another up counter for determining the portion of each cycle of the input clock signal that is high. A clock manipulation circuit receives each counter's value, and may be set to perform a fixed transform on the input clock signal, such as clock delay/advance, duty cycle shifting, and frequency multiplication/division. The clock manipulation circuit output values are loaded into two down counters that are also clocked by the internal clock. On the rising edge of the input clock signal, the first down counter starts decrementing until the counter reaches zero, indicating that the desired delay interval has passed, at which point the delayed output clock signal is taken high. The second down counter then starts decrementing for an interval that is equal to the desired duty cycle of the output clock signal. When the second down counter reaches zero, the output clock signal is taken low, and the process repeats.