Semiconductor apparatus and method of manufacturing the same

Abstract

In a semiconductor memory apparatus having a cell array structure wherein occurrence of leak current is reduced and a margin at the time of sensing is increased, a plurality of memory transistors arranged in a matrix and having any one of four thresholds constitute banks in a column direction. The banks constitute memory cell arrays. A main bit line of Al is connected to three sub-bit lines via first selection transistors. A main ground line of Al is connected to two sub-ground lines via second selection transistors. Bank selection lines and word lines are formed to cross the main bit line and main ground line. Gates of the selection transistors are connected to the selection lines, and one selection line is connected to one selection transistor. Each of the sub-bit lines and sub-ground lines has a column of memory transistors which constitute a bank. A separation region (not shown) of a silicon oxide film, etc. is formed between the memory cell arrays to prevent leak current. Thereby, an information amount per one element can be made equal to a plural-bit information amount, and the bit data capacity can be increased.