The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 1996
Filed:
Apr. 03, 1995
William H Herndon, Sunnyvale, CA (US);
MicroUnity Systems Engineering, Inc., Sunnyvale, CA (US);
Abstract
A bias generation and distribution system in which bias potentials are generated at one main location within a logic circuit and then distributed throughout the logic circuit to MOS load devices, MOS load networks, other bias voltage conversion centers, and logic circuits is disclosed. The system generates a first bias voltage that provides a temperature compensated voltage that is utilized to bias MOS load devices and parallel MOS load networks. The first bias voltage generator includes either a reference MOS load device or a reference parallel MOS load network which determines the value of the first bias voltage. The reference MOS load network includes a switching network responsive to a first set of control signals. The first set of control signals may be adjusted to vary the value of the first bias voltage to compensate for process variations. The first bias voltage is distributed to either remote single load MOS devices or to remote parallel MOS load networks. The remote load networks also include switching networks responsive to a second set of control signals. The second set of control signals may be varied to determine the resistivity of the remote MOS load networks depending on the value of the first bias voltage. The system also generates a second temperature compensated bias voltage that is utilized along with the first bias voltage to bias remote bias conversion circuits. The remote conversion circuits generate a third bias voltage that is utilized, along with the first bias voltage, to bias remote logic gates. The first bias voltage biases the MOS resistive load of the logic gate and the third bias voltage biases the MOS current device of the logic gate. The second bias voltage generator and the remote conversion circuits are implemented with controllable switching networks so that current and logic swing adjustments of the logic gate may be performed.