The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 1996
Filed:
May. 15, 1995
Yoshio Hirose, Kawasaki, JP;
Koichi Yamashita, Kawasaki, JP;
Shigeki Kawahara, Kawasaki, JP;
Shinji Sato, Atsugi, JP;
Takeshi Sasaki, Kawasaki, JP;
Ataru Kumagai, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A semiconductor integrated circuit device provides; a master chip including a basic cell region having a plurality of basic cell arrays arranged thereon, for forming various kinds of circuits. An input/output cell region provides a plurality of input/output cells arranged along the periphery of the basic cell region. A first wiring layer is formed on the basic cell region and the input/output cell region via a first insulation layer and has contact holes at predetermined positions. The first wiring layer includes fixed wirings irrespective of the kind of circuit to be formed. A second wiring layer is formed on the first wiring layer via a second insulation layer having through holes at predetermined positions. The second wiring layer includes programmed wirings to specify the kind of circuit to be formed. Only the wiring pattern of the second wiring layer is suitably changed in accordance with the kind of circuits to be formed and connected among the input/output cell region, basic cell regions in regions corresponding to the input/output cell regions and the basic cell region, thereby greatly reducing a turnaround time of the device.