Data processor with enhanced error recovery

Abstract

Error detection and recovery is provided in a processor of small size and which can be integrated on a single chip by providing buffers for both data and processor status codes in order to contain errors until a subsequent check point preferably generated at the termination of each instruction is reached without detection of an error. Retry of an instruction can therefore be initiated using the status and data validated at the termination of the previous check point and without placing error correction processing in any critical path of the processor. Error detection is accomplished by comparing outputs of at least a pair of unchecked processors for both memory access requests and output data and status codes. Input to the processors is subjected to a parity check and parity check bits are generated for memory access requests. Error correcting codes are generated for data and status codes to allow correction of single bit errors during transmission within the processor or at a storage system. When an error is detected, all data which has not been validated, preferably by changing the logical value of a flag bit associated with each code, at the most recently generated check point is erased. Data codes in which the flag bit has been changed may be transferred to a storage system autonomously even after an error has occurred.