The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 1996
Filed:
May. 16, 1995
Robert J Inkol, Orleans, CA;
Abstract
A digital quadrature demodulator for an intermediate frequency (IF) input signal with an analog-to-digital (A/D) converter having a sampling frequency f.sub.s and an input to which the IF input signal is applied where the IF input signal has a bandwith B<f.sub.s /4 centered about a frequency of f.sub.s /4. The demodulator includes an arrangement to direct even numbered output signals from the A/D converter to an inphase channel and odd numbered output signals from the A/D converter to a quadrature channel where each channel contains a highpass filter and the demodulator includes circuits to decimate by 4 signals of the channels to generate, together with the filters, a quadrature output signal Q(nT) at an output of the quadrature channel and an inphase output signal I(nT) at an output of the inphase channel. The quadrature highpass filter in the quadrature channel has an optimized transform architecture in which the filter coefficients h.sub.k correspond to those of a lowpass prototype filter with N=2k+1 coefficients after multiplication by sin(k.pi./2) where k identifies a particular stage of the filter. The inphase highpass filter in the inphase channel has an optimized transform architecture in which the filter coefficients h.sub.k correspond to those of a lowpass prototype filter after multiplication by cos(k.pi./2). Employing optimized filter architectures and simplified filter coefficients obtained with a new design procedure provides a practical quadrature demodulator design which can be economically implemented in hardware.