Method for fabricating semiconductor memory devices

Abstract

A method for fabricating a semiconductor memory device including a matrix of memory cells each constituted by one transistor and one capacitor and capable of obtaining a large capacitance for achieving a high integration and yet maintaining superior characteristics of its elements. The method includes the steps of: (a) forming a transistor gate electrode in a portion of an insulating layer formed over a semiconductor substrate, in a buried manner; (b) forming a trench in the semiconductor substrate through a portion of the insulating layer; and (c) forming a transistor channel region, a source, a drain and a capacitor storage node, as a single layer, over a region defined over a transistor gate electrode-buried portion of the insulating layer and a region defined in the trench. Thereby a source, a drain and a gate channel of each transistor and a capacitor storage node are formed by a single layer. With this structure, a minimum information transmitting path is obtained, thereby enabling the overall structure and the fabrication therefor to be simplified. Furthermore, this method makes it easy to form an active region where elements are formed, without using an element isolation process, and thus overall fabrication becomes simplified.