Dual digital phase locked loop clock channel for optical recording

Abstract

A digital phase lock loop channel is provided for threshold detection of a pulse width modulated binary data stream that has negative and positive transitions defining one binary state of the data stream. A threshold-establishing and transition-detecting network receives this data stream and provides a first output of one polarity corresponding to the detection of a positive transition, a second output of an opposite polarity corresponding to the detection of a negative transition, and a time-of-arrival output corresponding to a positive and a negative transition. A first and a second digital PLL is provided, each PLL having a transition input, a time-of-arrival input, a phase-error input, a phase error output a data-valid output, and a data output. Each PLL has an internal digital phase detector network connected to receive its transition input and its time-of-arrival input, and each PLL is operable to generate the phase error output therefrom. Each PLL has an internal digital loop filter connected to receive the phase error output generated by its phase detector network, and to receive the phase error output that is generated by the other PLL. The output of the loop filter of each PLL is connected to the data-valid and data outputs of its respective PLL.