The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 1996

Filed:

Aug. 31, 1994
Applicant:
Inventors:

Sungwon R Moh, Wilton, CT (US);

Scott T Potter, Southport, CT (US);

Frank D Ramirez, Stamford, CT (US);

Edilberto I Salazar, Brookfield, CT (US);

Assignee:

Pitney Bowes Inc., Stamford, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02P / ;
U.S. Cl.
CPC ...
318254 ; 318439 ; 388811 ;
Abstract

A circuit for controlling a current in a load, the circuit includes: structure for connecting the circuit to a source of power, the power source connecting structure including a power switch having off and on operating modes; structure for connecting the circuit to a supply of a pulse width modulated (PWM) control signal, the PWM supply connecting structure including an AND gate having first and second input structure and an output structure, one of the first and second input structures connected for receiving the PWM control signal, and the AND gate output structure connected to the power switch for operating the switch; structure for monitoring the current in the load, the monitoring structure including a differential amplifier, the differential amplifier having an instantaneous output voltage signal proportional to the load current when the power switch is in the on operating mode, structure for comparing a value derived from the instantaneous signal to a high reference voltage signal and a low reference voltage signal and providing a first comparison signal, structure for providing a peak reference voltage signal in response to the first comparison signal, structure for comparing the peak reference voltage signal and instantaneous output voltage signal and providing a second comparison signal; and structure for providing a signal corresponding to the second comparison signal to the other of the first and second input structures of the AND gate for operating the power switch in consideration of the comparison between the peak reference voltage signal and instantaneous output voltage signal.


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