Fractional bit-leaking clock signal resynchronizer for a high-speed

Abstract

A method and apparatus are provided for smoothing jitter in a smoothed clock output by routing a portion of the incoming clock signal representing phase hit information through a digital high-pass filter (12), which produces complementary output digital signals. One of the output signals includes the higher order bits of the filtered phase hit signal, and the other output signal includes the lower order bits of the filtered phase hit signal. The filtered, complementary phase hit signals are summed with the stream of clock pulses to be smoothed. Each of these summed signals is supplied to a separate phase detector circuit (120, 121). The phase detector (120) receiving the higher order bit signal generates a coarse error signal, and the phase detector (121) receiving the lower order bit signal generates a fine error signal. These fractional coarse and fine error signals are summed and converted to a high resolution analog control signal which drives a voltage controlled oscillator (50) in a phase-locked loop circuit. The phase-locked loop functions as a type two, second order low-pass filter and generates the smoothed clock output signal. An elastic buffer (18) is used to time-coordinate the incoming data signals and the smoothed clock signals output from the resynchronizer circuit (100). The phase hit adjustments are thus low-pass filtered by the phase-locked loop, which is controlled by the high resolution analog signal. Consequently, the effects of these phase adjustments on the smoothed clock output signal are introduced slowly and more evenly over a relatively longer period of time, which significantly reduces jitter as compared to existing techniques.