The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 1996
Filed:
Mar. 13, 1995
Toshiaki Kirihata, Wappingers Falls, NY (US);
Shuso Fujii, Hopewell Junction, NY (US);
Yohji Watanabe, Fishkill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Kabushiki Kaisha Toshiba, , JP;
Abstract
A fault-tolerant DRAM design minimizes current flow in the even of a cross-fail. A bit-line precharge current limiter is provided for the bit-line precharge equalizer circuit. The bit-line precharge current limiter is both simple and effective, requiring very little silicon area to implement. The current limiter provides self current-limiting for defective bit-lines, without the necessity for a reference cell.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile