The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 1996

Filed:

Oct. 26, 1994
Applicant:
Inventor:

Takao Ichihara, Kawasaki, JP;

Assignee:

Fuji Electric Co., Ltd., Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05B / ;
U.S. Cl.
CPC ...
363 37 ; 363 97 ; 363131 ; 323283 ;
Abstract

An inverter device with a circuit for generating pulse width modulation (PWM) signal is formed of an inverter section and a circuit. The circuit includes an U/D counter 4 for regulating a control cycle of a PWM waveform, a register 1C for storing on-timing information of the PWM waveform, and a register 1D for storing off-timing information of the PWM waveform. The circuit is actuated by one of first and second modes. In the first mode, the PWM waveform is outputted by comparing an output of the counter 4 with the respective outputs of the registers 1C, 1D. In the second mode, the counter 4 counts down a signal, and after reaching zero, the counter counts up again, which is made within one cycle and is compared with only the output of the register 1C to output the PWM waveform. In the second mode, the reset level is not calculated, so that load to CPU is relieved, and the carrier cycle is shortened.


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