The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 1996
Filed:
Sep. 20, 1994
David B Parlour, Pittsburgh, PA (US);
F Erich Goetting, Cupertino, CA (US);
Stephen M Trimberger, San Jose, CA (US);
Edel M Young, Palo Alto, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
For antifuse programmable integrated circuit devices, in particular FPGA devices, the invention allows for alternative routing around antifuses which fail to program. The chip architecture includes wiring segments and antifuses which together allow for alternative routes around every antifuse in the event of failure of that antifuse. The method includes programming the device under control of a computer which can recalculate routes in the event of an antifuse which fails to program. Preferably the initial routing distributes unused wiring segments through the chip to be available for routing around a failed antifuse. When a failure occurs, the method includes determining an alternative route around every failed antifuse. The alternative route may be established directly after the antifuse has failed or after all initially selected antifuses have been programmed. The method also includes swapping of logic cell inputs, logic cells, and/or logic blocks from their original layout to adapt to a failed antifuse without changing the timing of signals which would have used the failed antifuse.