High performance computer system which minimizes latency between many

Abstract

A new machine design minimizes latency between many high performance processors and a large amount of shared memory. Wire length, latency and skew are minimized by stacking edge connected modules (ECMs). The ECMs are characterized by signal input/output (I/O) pads on three edges, the two opposing inside connector edges and the third global connector edge. The ECMs support multiple processors per module, a plurality of basic storage modules (BSMs) per module, and portions of request and response switches per module. A plurality of processor ECMs and request switch ECMs are stacked in a first stacks and a plurality of BSM ECMs and response switch ECMs are stacked in a second stack. The two stacks are arranged adjacent one another with the request switch ECMs above or below the processor ECMs and the response switch ECMs below or above the BSM ECMs so that the response switch ECMs are adjacent the processor ECMs and the request ECMs are adjacent the BSM ECMs. The data flow from a processor to addressed memory and back to the processor is unidirectional about a loop defined by connections on the inside edges of the ECMs. The stacks as described form a subsystem which may be used as a stand-alone system or interconnected with other subsystems via the global connectors connected to the third edges of the ECMs. The global connectors allow the processors of one subsystem to be connected to the BSMs of another subsystem.