The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 1996
Filed:
Jul. 21, 1994
Akihide Ogawa, Nagasaki, JP;
Hiroshi Yamagata, Kanagawa, JP;
Kazuhiro Takeda, Nagasaki, JP;
Yoshiharu Ito, Tokyo, JP;
Sony Corporation, , JP;
Abstract
Reductions in size and cost for a sync chip clamping/sync separation circuit are envisaged by the use of the CMOS process. The final output amplification section of a differential amplifier circuit is implemented as a P channel FET, and the pull down current for the drain terminal of this P channel FET is set to a value which is smaller than the current which flows when this P channel FET is ON. A constant voltage is supplied by resistors to the non inverting input terminal (+) of the differential amplification circuit. Further, the inverting input terminal (-) of the differential amplification circuit and the output terminal thereof are connected, and also an input coupling capacitor is interposed between the inverting input terminal (-) thereof and an video signal input terminal. Further, a buffer is provided which takes out a sync signal from an input of the P channel FET.