The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 1996
Filed:
Apr. 12, 1994
Juha Rapeli, Oulu, FI;
Nokia Mobile Phones Ltd., Salo, FI;
Abstract
The present invention relats to a method for processing a signal, and a signal processing circuit according to the method, in which circuit one or two transistors (T1, T2) switched according to the switches are used as the active member of the entire circuit, the charge passing through said transistors being controlled, in addition to the switches, by the transferrable charge itself so that on concluded transfer of charge, all current flow in the circuit stops by itself. By means of the present invention, the signal processing is, irrespective of the polarity of the signal (positive or negative) and of the threshold voltages (Uth1, Uth2) of the transistors, linear because the signal voltage (U.sub.s) is produced, as taught by the invention, relative to a reference voltage (U.sub.Ref) of predetermined magnitude in that a sum of the signal voltage (U.sub.s) and said reference voltage (U.sub.Ref) is produced and the polarity of said sum is every time the same as the polarity of the reference voltage (U.sub.Ref), irrespective of the variation of the signal voltage (U.sub.s), and when charge samples proportional to the signal voltage (U.sub.s) are taken, a quantity thereof is taken which is proportional to the sum (U.sub.s + U.sub.Ref) of the signal voltage (U.sub.s) and the reference voltage (U.sub.Ref), whereby the charge samples pro-portional to said sum (U.sub.s + U.sub.Ref) are transferred to the integrating capacitance (C.sub.o) included in the circuit, and thereafter, a quantity of charge samples proportional to the reference voltage (U.sub.Ref) is added into the integrating capacitance (C.sub.o) with an opposite polarity relative to the polarity of the charge samples proportional to said sum (U.sub.s + U.sub.Ref).