Power-out reset system

Abstract

A power-out reset circuit includes reference voltage and current generators to generate a reference voltage and a reference current which are essentially independent of temperature variations over a useful temperature range, a delay/disable circuit, over and under voltage detectors and output logic circuitry. This circuit detects when the voltage level of a supply voltage source (+VDD) exceeds preselected limits. The reference voltage, which is related to the silicon band gap voltage, is connected to a first input of a comparator of each of the voltage detectors. The reference current, which is derived from the silicon band gap voltage, is connected to a current source of each of the detectors. Each detector has a hysteresis circuit which changes the point at which the comparator switches in the event that +VDD crosses into or outside of a preselected operating range. The delay/disable circuit ensures that the reference voltage is stable before the voltage detectors are activated, and that the voltage detectors are disabled when the supply voltage source falls below a minimum value which causes the reference voltage to be invalid (i.e., to be outside the preselected operating range. Outputs of the comparators are coupled to the output logic circuitry. The output logic circuitry includes a two input EXCLUSIVE OR logic circuit, a delay circuit, a two input OR logic gate, a transistor, a two input NOR logic gate, and an inverter.