Central processor with duplicate basic processing units employing

Abstract

In order to validate data manipulation results in a CPU which incorporates duplicate basic processing units or integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation to obtain first and second data manipulation results, which should be identical, and a cache unit for receiving data manipulation results from both BPUs and for transferring specified information words simultaneously to both BPUs upon request. These operations are controlled by cache interface control signals identically generated in each BPU. In each BPU, the control signals are arranged into first and second groups which are nominally identical. The first control signal group is transmitted to the cache unit from one BPU while the second control group is transmitted to the cache unit from the other BPU. In each BPU, parity is generated for each control group separately. Parity for the group sent to the cache unit by each BPU is included with the control signal information for checking in the cache unit. Parity for the group not sent to the cache unit by each BPU is transmitted to the other BPU and checked against the locally generated parity for that group. In the event of a parity miscompare sensed in either BPU or a parity error sensed in the cache unit, an error signal is issued to institute appropriate remedial action.