The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 1996

Filed:

Jan. 15, 1991
Applicant:
Inventor:

Paul A Winser, Redhill, GB;

Assignee:

U.S. Philips Corporation, New York, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395130 ;
Abstract

A display apparatus includes a host processor (14) with associated main memory (24) and a display processor with associated display memory (30) and texture memory (41'). The host processor includes an arrangement (18) for storing in the texture memory (41') at least one pyramidal or part-pyramidal array of texel values representing a given texture at at least two levels of resolution defined by respective values of a level coordinate (L) and an arrangement (18) for supplying object primitive data to the display processor (28',49). The display processor includes a processing unit (28') for generating from the object primitive data a series of pixel addresses (X,Y) for application to the display memory (30) and a corresponding series of 2-D texture coordinate pairs (U,V) each with an associated level coordinate (L), to effect a mapping of the stored texture onto the object primitive at a level or levels of resolution defined by the level coordinate (L). The texture memory includes a linearly addressed (one-dimensional) texture memory (41'). The arrangement for storing the pyramidal or part-pyramidal array of texel values includes an arrangement (D1) for storing each 2-D array thereof in linear form in the texture memory (41'). A texture management circuit (49) includes circuitry (50) for receiving and storing page location information (SWI1,W1,B1) for locating each such array in the texture memory. The texture management circuit (49) further includes circuitry (50 to 63) for using the stored page location information to convert the received texture coordinate pair (U,V) and level coordinate (L) into a linear physical texture memory address (A1).


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