Counter cell and counter circuit

Abstract

A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The latch circuit is formed of a first clocked half-latch, a second clocked half-latch and an inverter for storing a binary output signal. The first clocked half-latch is responsive to a first clock phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch is responsive to a second clock phase signal for transferring a binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The control circuit requires only one transistor and two input signals to perform its required functions. When the input complement signal is High and the first phase input clock signal is High, an enable signal is sent to the first clocked half-latch, thereby enabling the count process. Any number of these counter cells can be arranged to form an N-bit counter circuit.