The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 1996

Filed:

Sep. 27, 1994
Applicant:
Inventors:

Chitra K Subramanian, Austin, TX (US);

Gerold W Neudeck, West Lafayette, IN (US);

Assignee:

Purdue Research Foundation, West Lafayette, IN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 34 ; 437 41 ; 437 62 ; 437 90 ;
Abstract

A method of forming a semiconductor-on-insulator (SOI) electronic device includes the steps of etching a semiconductor substrate to form a plurality of adjacent trenches therein and then forming electrically insulating layers on bottoms of the trenches. Epitaxial lateral overgrowth (ELO) is then performed to grow respective monocrystalline semiconducting regions in the trenches. These semiconducting regions are preferably grown from a sidewall of each trench onto a respective insulating layer and fill each trench. Monocrystalline active regions of the electronic device are then formed in the semiconducting regions and also in the substrate, adjacent the trench sidewalls. For example, a monocrystalline trench isolated extrinsic base region of a bipolar junction transistor (BJT) can be formed in a semiconducting region in a respective trench, and a corresponding intrinsic base region and an intrinsic collector region can be formed in the substrate, adjacent the semiconducting region. Alternatively, trench isolated source and drain regions of a field effect transistor (FET) can be formed in one or more adjacent semiconducting regions and the corresponding channel region of the FET can be formed therebetween.


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