The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 1996
Filed:
May. 03, 1994
Brian T Soderberg, Woodinville, WA (US);
Dale D Miller, Seattle, WA (US);
Douglas Pheil, Redmond, WA (US);
Kent Cauble, Renton, WA (US);
Mark N Heinen, Issaquah, WA (US);
Mark L Kenworthy, Duvall, WA (US);
Loral Aerospace Corp., New York, NY (US);
Abstract
An image generator architecture in which tri-level fixed interleave processing provides medium grain parallelism for polygon, tiling, and pixel operations. Input data at each stage are divided into spatially distributed subsets that are interleaved among parallel processors using a fixed, precalculated mapping that minimizes correlation of local scene complexity with any one processor. The present tri-level fixed interleave processing architecture divides a processing task into a pseudo-random, fixed interleaved pattern of regions that are assigned to different processors. Each processor processes many of these randomly located regions. The assignment of processors to regions is a fixed repeating pattern. The highest level of fixed interleave processing is the allocation of fixed-size database regions (area modules) to polygon processors. The next level relates to image sub-region fixed interleave processing. At this level, the displayed image is divided into small sub-regions that are assigned to tilers in a pseudo-random, but fixed manner. This levels the load across all pixel processors. Typically, tilers process a large contiguous area of the image. The present invention uses small sub-regions (64.times.64 pixels) and assigns many sub-regions from different channels to a single tiler. Each tiler maintains equal loading .even with localized regions of high pixel processing. The third level relates to two-by-two pixel, fixed interleave processing. The image is further divided into 2.times.2 pixel blocks spread across multiple pixel operators on a tiler. This fine grain parallelism, in a fixed pseudo-random orientation, ensures equal loading across all pixel processors. The second aspect of the present invention is the use of polygon and pixel distribution buses. Maximum image generator configurability, expansion, and efficient processing is required for a variety of simulator configurations used in networked training environments. To accomplish this, distribution buses are implemented between all graphics processing stages.